Design Pipeline SHA-3 MIPS Processor using FPGA
May S. Al-Rabi
The purpose of this study is to implement and evaluate the security of the Keccak hash function in a Microprocessor without Interlocked Pipelines (MIPS) processor using Field Programmable Gate Arrays (FPGA). The design methodology involves selecting a set of instructions that are required to run the SHA-3 Keccak algorithm on the MIPS processor. The findings of this study demonstrate that the Keccak hash function can be efficiently implemented on a MIPS processor using FPGA technology. The research limitations include the fact that the study only focuses on the implementation of the Keccak hash function on a MIPS processor using FPGA, and does not consider other platforms or technologies. The practical implications of this study are that it provides a cost-effective solution for implementing secure hash functions on embedded systems that require low power consumption and high performance. The originality and value of this study lie in its contribution to the field of cryptography by demonstrating the feasibility of implementing secure hash functions on low-cost processors using FPGA technology.
Key words: VHDL, MIPS Processor, SHA-3, Keccak, FPGA.
|Title:||Design Pipeline SHA-3 MIPS Processor using FPGA|
May S. Al-Rabi
|Journal Name:||Journal of Scientific Reports|
|Date of Publication:||27/10/2023|
|Paper Type:||Research Paper|
Cite This Article:
May S. Al-Rabi (2023). Design Pipeline SHA-3 MIPS Processor using FPGA. Journal of Scientific Reports, 5(1), 69-77. doi: https://doi.org/10.58970/JSR.1027
Retrieved from https://ijsab.com/wp-content/uploads/1027.pdf
About Author (s)
May S. Al-Rabi, Computer science department, University of technology, Iraq.